Virtual Event | January18-19, 2023
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Wednesday, January 18 • 7:33am - 7:43am
Feature Optimizations for RISCV Compliance Test Generator (CTG) and RISCV ISA Coverage (ISAC) - Edwin Joy, Incore Semiconductors Pvt. Ltd. & Priyansh Rathi

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The project involved feature additions and optimizations to the RISC-V Architectural Compatibility Testing Ecosystem through the spring and fall terms of the RISC-V LFX mentorship program. The main feature improvements to the RISC-V ISAC are the design of a RISC-V disassembler using the encoding scheme maintained by a RISCV GitHub repository and re-architecting the codebase to ease adding support for future RISC-V extensions. RISCV-CTG has now been equipped with the infrastructure necessary for the generation of interesting tests to help discover pipelining hazards in the RISC-V implementation. It also facilitates the generation of CSR-combination coverpoint tests to check compliance with the privileged part of the RISC-V spec. Edwin and Priyansh with the guidance of their mentors, helped them imbibe a 'future-proof' software design philosophy practiced throughout the ecosystem. It was through this project that they came across a multitude of fascinating RISC-V initiatives and open-source contributions. They could amass sufficient experience in RISC-V, advanced Python programming and various software design practices through this mentorship program.

avatar for Edwin Joy

Edwin Joy

Verification Engineer, Incore Semiconductors Pvt. Ltd.
Edwin Joy is a graduate from Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Sikkim, India. He currently works as a Verification Engineer at InCore Semiconductors. He has been an active open-source contributor to the RISC-V Architectural... Read More →

Wednesday January 18, 2023 7:33am - 7:43am EST